In view of the rapid spread of intelligent devices such as computers, semiconductor devices are being rapidly developed. Semiconductor devices are now being required to have high storage-capacity and to operate at high speed. To meet these requirements, technologies for manufacturing semiconductor devices are being developed with an eye toward improving the degree of integration, the reliability, and the response rate of the semiconductor devices.
Generally, semiconductor memory devices are divided into volatile and nonvolatile memory devices. Examples of nonvolatile memory devices include a flash memory device, a McRAM device, etc. The McRAM device includes a first gate electrode functioning as a flash memory and a second gate electrode functioning as a normal gate electrode in a single cell. The McRAM device has recently been in the spotlight due to its advantages (e.g., low power dissipation, low manufacturing cost, and rapid speed of information processing).
FIGS. 1 through 4 are cross-sectional views illustrating a conventional prior art process for fabricating a McRAM device.
Referring to FIG. 1, a substrate 1 including an active region 2 and a non-active region 3 is provided. A dielectric layer 5, a first conducting layer 7, and an insulating layer 9 are sequentially deposited on the substrate 1. Then, a mask pattern 4 is formed over the insulating layer 9.
Referring to FIG. 2, some parts of the insulating layer 9, the first conducting layer 7, and the dielectric layer 5 are sequentially removed through an etching process using the mask pattern 4 as an etching mask. As a result, a first gate electrode 10 comprising an insulating layer pattern 9a, a first conducting layer pattern 7a, and a dielectric layer pattern 5a is formed on the active region 2 of the substrate 1. The first gate electrode 10 functions as a flash memory. Next, an oxide layer 11 and a nitride layer 13 are sequentially deposited on the substrate 1 and the first gate electrode 10.
Referring to FIG. 3, the nitride layer 13 and the oxide layer 11 are removed by an etch back process to form spacers 14. The spacers 14 comprise an oxide pattern 11a and a nitride pattern 13a on sidewalls of the first gate electrode 10. The nitride pattern 13a may impose stress on the first conducting layer pattern 7a of the first gate electrode 10, although it can effectively prevent a silicide layer from being formed in following processes. Therefore, in forming the spacers 14, the oxide layer 11, which mitigates the stress more or less, is first deposited and, then, the nitride layer 13 is deposited on the oxide layer 11.
Referring to FIG. 4, another oxide layer 15 is deposited on the substrate 1, but the oxide layer 15 is not deposited on the first gate electrode 10 or the spacers 14. Then, a second conducting layer 17 is deposited over the oxide layer 15, the first gate electrode 10, and the spacers 14. A residual insulating layer, which remains on the active region 2 after the formation of the first gate electrode 10, has to be completely removed prior to the deposition of the oxide layer 15. The residual insulating layer is removed by wet etching. However, when the insulating layer is removed, a portion of the oxide pattern 11a of the spacers 14 may also be removed by the etching process. In addition, if the first conducting layer pattern 7a is exposed through an etched part “A” of the spacers 14, a bridge between the first conducting layer pattern 7a and the second conducting layer 17 may occur. Therefore, in fabricating a first gate electrode and a second gate electrode which functions as a normal gate electrode, conventional methods frequently cause device defects due to deterioration in the insulation capability.
The prior art Shone et al., U.S. Pat. No. 5,618,742, describes a method of making a flash EPROM with conductive sidewall spacers contacting a floating gate. The method for fabricating a plurality of flash EPROM transistors according to the above-mentioned U.S. Patent comprises forming a floating gate insulating layer over a substrate; defining a plurality of strips of polysilicon in a first polysilicon layer over the floating gate insulating layer; exposing the substrate to dopants; annealing the substrate to drive the dopants into the doped regions; forming a thicker insulator with an insulating material over buried diffusion regions; exposing the plurality of strips of polysilicon; depositing a second polysilicon layer over and in contact with the plurality of strips; etching the second polysilicon layer for a time to form self-aligned conductive spacer lines; forming a control gate insulator over the plurality of strips and the conductive spacer lines; depositing a third polysilicon layer over the control gate insulator; and etching the third layer, the conductive spacers, and the plurality of conductive strips to define control gate conductors and floating gates.